New Logical Architecture of Wallace Tree Encoder, with Reduced Computations as well as Auto-detection of Bubble Error in Flash ADC
By: Roy, Anirban
.
Contributor(s): Satish Kumar.
Publisher: New Delhi Journals Pub 2019Edition: Vol.5(2), Jul-Dec.Description: 1-14p.Subject(s): EXTC EngineeringOnline resources: Click here
In:
International journal of wireless network securitySummary: Speed is the major bottleneck of any flash ADC (analog-to-digital converter), which arises out from the nature computation that one ADC has to undergo at its different phases. In flash ADC one major component is the conversion of thermometer code to binary code. With the increase of operating frequency, error may occur in thermal to binary conversion, which is termed as bubble error. A new logical structure is proposed herewith, which reduces the number of computations by 40% with inherent ability of auto-detection and compensation of 1st order bubble error as well a certain type of 2nd order bubble errors.
| Item type | Current location | Call number | Status | Date due | Barcode | Item holds |
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Articles Abstract Database
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School of Engineering & Technology Archieval Section | Not for loan | 2021-2021184 |
Speed is the major bottleneck of any flash ADC (analog-to-digital converter), which arises out from the nature computation that one ADC has to undergo at its different phases. In flash ADC one major component is the conversion of thermometer code to binary code. With the increase of operating frequency, error may occur in thermal to binary conversion, which is termed as bubble error. A new logical structure is proposed herewith, which reduces the number of computations by 40% with inherent ability of auto-detection and compensation of 1st order bubble error as well a certain type of 2nd order bubble errors.
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